An SOI structure consists of a top semiconductor layer, a substrate layer and a buried dielectric layer interposed between the top semiconductor layer and the substrate layer, where said top semiconductor layer is called active layer and said substrate layer is a semiconductor layer or dielectric layer. Semiconductor devices and circuits are formed in said active layer. In integrated circuits, high-voltage devices and low-voltage circuitry are isolated by isolation trench 30, while said active layer 3 and substrate layer 1 are isolated by dielectric layer 2, as shown in FIG. 1. Therefore, compared with bulk silicon (semiconductor) technology, SOI technology offers lots of advantages, such as weakened parasitic effect, low leakage current, high integration and hard resistance to radiation and free from controllable silicon latch-up effect. These advantages enable it to be widely applied in high-speed, high temperature, lower power loss and resistance to radiation fields.
The targets of SOI power integrated circuit are to realize a high breakdown voltage, low power loss and effective isolation between high-voltage unit and low-voltage unit. Lateral SOI devices, such as LDMOSFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor), become the key components of SOI power integrated circuits because of its ease integration and low on-resistance. The lateral SOI devices have attracted much attention in plasma display panel, motor drives, automotive electronics, portable power management products, personal computers and so on. And lateral MOSFET is widely applied to RF field because of its higher switching speed than that of VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor).
For conventional LDMOSFET devices, the drift region length monotonically increases with an increasing breakdown voltage (BV). This makes device (or circuit) chip area and cost increase, and also it is adverse to miniaturization of chip. Furthermore, the on-resistance (Ron) increases with an increase in BV (or drift region length) by the relationship Ron∝BV2.5. The increase in Ron leads to an increase in power loss and decrease in switching speed.
Compared with planar gate MOSFETs, trench gate MOSFETs can increase packaging density and increase channel density and current density; On the other hand, it is easy to fabricate a shorter channel because the channel length is not limited by lithography process in trench gate MOSFETs. Both of them reduce Ron and increase current capacity of trench gate MOSFETs. Furthermore, trench gate MOSFETs can eliminate the JFET (Junction Field-Effect-Transistor) effect and latch-up effect.
To solve these issues mentioned above in the conventional LDMOS, Trench-type SOI LDMOS structures were proposed owing to advantages of trench MOSFETs. In reference (Won-So Son, Young-Ho Sohn, Sie-Young Choi, “Effects of a trench under the gate in high voltage RESURF LDMOSFET for SOI power integrated circuits”, Solid-State Electronics, 2004, 48, 1629-1635), the RESURF LDMOS with an trench was proposed. The device structure is shown in FIG. 2. Oxide trench 31 is introduced in drift region from the end of gate electrode G to the drain region. When the doping concentration is high, said oxide trench 31 reduces the high electric field at the surface of silicon under the gate electrode G to prevent breakdown here, and reduces the surface peak electric field at the drain side, thereby increases the breakdown voltage and reduces the specific on-resistance. The maximum breakdown voltage 356V had been achieved with the 16 μm drift region length, on 8 nm active layer 3, over 3 μm buried dielectric layer 2. BV=352V and specific on-resistance is 18.8 mΩ·cm2 were obtained by experiment in this reference. Specific on-resistance is 9 mΩ·cm2 for the proposed LDMOSFET at BV=250V. It can be seen that the effect of this structure on reducing the drift region length and the specific on-resistance is limited.
A structure that drain electrode D and gate electrode G were placed in one step trench was proposed in reference (Naoto Fujishima and C. Andre T. Salama, “A trench lateral power MOSFET using self-aligned trench bottom contact holes”, IEDM 1997, 359-362), where a thicker sidewall oxide layer 32 is at the lower half of trench (near the drain). The structure is referred as Trench Lateral Power MOSFET with a trench bottom Drain contact (TLPM/D MOSFET). This device structure is shown in FIG. 3. In U.S. Patent (U.S. Pat. No. 7,005,352B2, 2006 Feb. 28, “trench-type MOSFET having a reduced device pitch and on-resistance”), the structure of Trench Lateral Power MOSFET with a trench bottom Source contact (TLPM/S MOSFET) was presented, where the source electrode S and gate electrode G were placed in one trench. The device structure is shown in FIG. 4. Both of TLPM/D MOSFET and TLPM/S MOSFET can reduce the pitch (or chip area) and on-resistance while maintaining a high BV. TLPM/D MOSFET is more suitable for the BV>80V MOSFET with a reduced resistance, while TLPM/S MOSFET is more suitable for the BV<80V MOSFET with a reduced pitch and resistance. The process for TLPM/D MOSFET is simpler. For the BV>100V TLPM/D MOSFET, the effect on reducing the pitch will be weakened with the increasing thickness of the thicker sidewall oxide layer 32 at the lower half of trench; meanwhile, it become difficult to fabricate the drain- and the gate-electrode in one deep and narrow trench as the trench depth increases with an increasing breakdown voltage. In these two structures, the drain- and the gate-electrode or the source- and the gate-electrode are required to fabricate in one trench, the process thereby becomes more difficult as BV increases (trench depth increases); moreover, the effect on reducing the pitch becomes weak with an increasing BV. The TLPM/S devices are used in IC in the U.S. Patent (US 2007/0298562A1, 2007 Dec. 27, “method of manufacturing a semiconductor integrated circuit device”). However, the various devices in IC are isolated by both PN junction isolation and shallow trench isolation (STI), and the source electrode and gate electrode of the high-voltage MOSFET are fabricated in the one trench. Its process thus is more complex.